1 of 10 features ? 10 years minimum data retention in the absence of external power ? data is automatically protected during power loss ? replaces 512k x 8 volatile static ram, eeprom or flash memory ? unlimited write cycles ? low - power cmos ? read and write access times of 70ns ? lithium energy source is electrically disconnected to retain freshness until power is applied for the first time ? full 10% v cc operating range (ds1250y) ? optional 5% v cc operating range (ds1250ab) ? optional industrial temperature range of -40 c to +85 c, designated ind ? jedec standard 32 - pin dip package ? powercap module (pcm) package - directly surface - mountable module - replaceable snap - on powercap provides lithium backup battery - standardized pinout for all nonvolatile sram products - detachment feature on pcm allows easy removal using a regular screwdriver pin assignment pin description a0 - a18 - address inputs dq0 - dq7 - data in/data out ce - chip enable we - write enab le oe - output enable v cc - power (+5v) gnd - ground nc - no connect ds1250y/ab 4096k nonvolatile sram www.maxim - ic.com 13 1 2 3 4 5 6 7 8 9 10 11 12 14 31 32 - pin encapsulated package 740- mil extended a14 a7 a5 a4 a3 a2 a1 a0 dq1 dq0 v cc a15 a17 we a13 a8 a9 a11 oe a10 ce dq7 dq5 dq6 32 30 29 28 27 26 25 24 23 22 21 19 20 a16 a12 a6 a18 dq2 gnd 15 16 18 17 dq4 dq3 1 nc 2 3 a15 a16 nc v cc we oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a17 a14 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 34 a18 gnd v bat 34- pin powercap module (pcm) ( uese ds9034pc + or ds9034pci+ powercap ) 19 - 564 7 ; rev 12/10 downloaded from: http:///
ds1250y/ab 2 of 10 description the ds1250 4096k nonvolatile srams are 4,194,304 - bit, fully static, nonvolatile srams organized as 524,288 words by 8 bits. each complete nv sram has a self - contained lithium energy source and control circuitry which constantly monitors v cc for an out - of - tolerance condition. when such a condition occurs, the lithium energy source is automatically switched on and write protection is uncondition ally enabled to prevent data corruption. dip - package ds1250 devices can be used in place of existing 512k x 8 static rams directly conforming to the popular byte - wide 32 - pin dip standard. ds1250 devices in the powercap module package are directly surface m ountable and are normally paired with a ds9034pc powercap to form a complete nonvolatile sram module. there is no limi t on the number of write cycles that can be executed and no additional support circuitry is requi red for microprocessor interfacing. read mode the ds1250 executes a read cycle whenever we (write enable) is inactive (high) and ce (chip enable) and oe (output enable) are active (low). the unique address specified by the 19 address inputs (a 0 - a 18 ) defines which of the 524,288 bytes of data is to be accessed. valid data wil l be available to the eight data output drivers within t acc (access time) after the last address input signal is stable, providi ng that ce and oe (output enable) access times are also satisfied. if oe and ce access times are not satisfied, then data access must be measured from the later - occurring signal ( ce o r oe ) and the limiting parameter is either t co for ce or t oe for oe rather than address access. write mode the ds1250 executes a write cycle whenever the we and ce signals are active (low) after address inputs are stable. the later - occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inactive (high) during write cycles to avoid bus contention. however, if the output drivers are ena bled ( ce and oe active) then we will disable the outputs in t odw from its falling edge. data retention mode the ds1250ab provides full functional capability for v cc greater than 4.75 volts and write protects by 4.5 volts. the ds1250y provides full functional capability for v cc greater than 4.5 volts and write pro tects by 4.25 volts. data is maintained in the absence of v cc without any additional support circuitry. the nonvolatile static rams constantly monitor v cc . should the supply voltage decay, the nv srams automatically write protect themselves, all inputs bec ome dont care, and all outputs become high - impedance. as v cc falls below approximately 3.0 volts, a power switching circuit connec ts the lithium energy source to ram to retain data. during power - up, when v cc rises above approximately 3.0 volts, the powe r switching circuit connects external v cc to ram and disconnects the lithium energy source. normal ram operation can resume after v cc exceeds 4.75 volts for the ds1250ab and 4.5 volts for the ds1250y. freshness seal each ds1250 device is shipped from maxim with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than 4.25 volts, the lithium ener gy source is enabled for battery back - up operation. downloaded from: http:///
ds1250y/ab 3 of 10 packages the ds1250 is available in two packages: 32 - pin dip and 34 - pin powercap module (pcm). the 32 - pin dip integrates a lithium battery, an sram memory and a nonvolati le control function into a single package with a jedec - standard 600 - mil dip pinout. the 34 - pin powercap module integrates sram memory and nonvolatile control into a module base along with conta cts for connection to the lithium battery in the ds9034pc powercap. the powercap module package design allo ws a ds1250 pcm device to be surface mounted without subjecting its l ithium backup battery to destructive high - temperature reflow soldering. after a ds1250 pcm module base is re flow soldered, a ds9034pc powercap is snapped on top of the pcm to form a complete nonvolatile sr am module. the ds9034pc is keyed to prevent imprope r attachment. ds1250 module bases and ds9034pc powercaps are ordered separately and shipped in separate containers. see the ds9034pc data sheet fo r further information. downloaded from: http:///
ds1250y/ab 4 of 10 absolute maximum ratings voltage on any pin relative to ground - 0.3v to +6.0v operating temperature commercial: 0c to +70c industrial: - 40c to +85c storage temperature edip - 40c to +85 c powercap - 55c to +125c lead temperature (soldering, 10 s) +260c soldering temperature (reflow, powercap) +260c note: edip is wave or hand soldered only. this is a stress rating only and functional operation of the device at these or an y other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum r ating conditions for extended periods of time ma y affect reliability. recommended dc operating conditions (t a : see note 10) parameter symbol min typ max uni ts notes ds1250ab power supply voltage v cc 4.75 5.0 5.25 v ds1250y power supply voltage v cc 4.5 5.0 5.5 v logic 1 v ih 2.2 v cc v logic 0 v il 0.0 +0.8 v dc electrical characteristics (v cc = 5v 5% for ds1250ab) (t a : see note 10) (v cc = 5v 10% for ds1250y) parameter symbol min typ max units notes input leakage current i il -1.0 +1.0 a i/o leakage current ce v ih v cc i io -1.0 +1.0 a output current @ 2.4v i oh -1.0 ma output current @ 0.4v i ol 2.0 ma standby current ce =2.2v i ccs1 200 600 a standby current ce =v cc -0.5v i ccs2 50 150 a operating current i cco1 85 ma write pro tection voltage (ds1250ab) v tp 4.50 4.62 4.75 v write protection voltage (ds1250y) v tp 4.25 4.37 4.5 v capacitance (t a = + 25 c) parameter symbol min typ max units not es input capacitance c in 5 10 pf input/output capacitance c i/o 5 10 pf downloaded from: http:///
ds1250y/ab 5 of 10 ac electrical c har ac te r is tic s (v cc = 5v 5% for ds1250ab) (t a : see note 10) (v cc = 5v 10% for ds1250y) parameter symbol ds1250ab-70 ds1250y-70 units notes min max read cycle time t rc 70 ns access time t acc 70 ns oe to output valid t oe 35 ns ce to output valid t co 70 ns oe or ce to output active t coe 5 ns 5 output high - z from deselection t od 25 ns 5 output hold from address change t oh 5 ns write cycle time t wc 70 ns write pulse width t wp 55 ns 3 address setup time t aw 0 ns write recovery time t wr1 t wr2 5 15 ns ns 12 13 output high - z from we t odw 25 ns 5 output active from we t oew 5 ns 5 data setup time t ds 30 ns 4 data hold time t dh1 t dh2 0 10 ns ns 12 13 downloaded from: http:///
ds1250y/ab 6 of 10 read cycle see note 1 write cycle 1 see notes 2, 3, 4, 6, 7, 8, and 12 downloaded from: http:///
ds1250y/ab 7 of 10 write cycle 2 see notes 2, 3, 4, 6, 7, 8, and 13 power - down/power - up condition see note 11 downloaded from: http:///
ds1250y/ab 8 of 10 power - down/power - up timing (t a : see note 10) parameter symbol min typ max units notes v cc fail detect to ce and we inactive t pd 1.5 s 11 v cc slew fr om v tp to 0v t f 150 s v cc slew from 0v to v tp t r 150 s v cc valid to ce and we inactive t pu 2 ms v cc valid to end of write protection t rec 125 ms (t a = + 25 c) parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning: under no circumstance are negative undershoots, of any amplitude, allo wed when dev ice is in battery backup mode. notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high - impedance state. 3. t wp is specified as t he logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t dh , t ds are measured from the earlier of ce or we going high. 5. these parameters are sampled with a 5 pf load and are not 100% tested. 6. if the ce low transition occurs simultaneously with or latter th an the we low transition, the output buffers remain in a high - impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the ou tput buffers remain in high - impedance state during this period. 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high - impedance state during this period. 9. each ds1250 has a built - in switch that disconnects the lithium source until the user first app lies v cc . the expected t dr is defined as accumulative time in the absence of v cc starting from the time power is fir st applied by the user. this parameter is assured by component selectio n, process control, and design. it is not measured directly during production testing. 10. all ac and dc electrical characteristics are valid over the full operatin g temperature range. for commercial products, this range is 0 c to 70 c. for industrial products (ind), this range is -40 c to +85 c. 11. in a power - down condition the voltage on any pin may not exceed the voltage on v cc . 12. t wr1 and t dh1 are measured from we goin g high. 13. t wr2 and t dh2 are measured from ce going high. 14. ds1250 modules are recognized by underwriters laborator ies (u l ) under file e99151. downloaded from: http:///
ds1250y/ab 9 of 10 dc test conditions ac test conditions outputs open output load: 100 pf + 1ttl gate cy cle = 200 ns for operating current input pulse levels: 0 - 3.0v all voltages are referenced to ground timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5 ns ordering information part temp range supply toleran ce pin - package speed grade (ns) ds1250ab-70+ 0c to +70c 5v 5% 32 740 edip 70 ds1250abp-70+ 0c to +70c 5v 5% 34 powercap* 70 ds1250ab- 70ind+ - 40c to +85c 5v 5% 32 740 edip 70 ds1250abp- 70ind+ - 40c to +85c 5 v 5% 34 powercap* 70 ds1250y-70+ 0c to +70c 5v 10% 32 740 edip 70 ds1250yp-70+ 0c to +70c 5v 10% 34 powercap* 70 ds1250y- 70ind+ - 40c to +85c 5v 10% 32 740 edip 70 ds1250yp- 70ind+ - 40c to +85c 5v 10% 34 powercap* 70 + denotes a lead (pb) - free/rohs - compliant p ackage . * ds9034pc + or ds9034pci + (powercap) required. must be o rdered separately. package information for the latest package outline information and land patterns, go to www.maxim - ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs sta tu s. package type package code outline no. land pattern no. 32 edip mdt32+6 21-0245 34 pcap pc2+5 21-0246 downloaded from: http:///
ds1250y/ab 10 of 10 revision histor y revision date description pages changed 121907 added the p ackage information table ; r emoved the dip module package drawing and dimension table 8 12/10 updated the storage information, soldering temperature, and lead temperature information in the absolute maximum ratings section; removed the -10 0 min/max information from the ac electrical chara cteristics table; updated the ordering information table (removed -10 0 parts and leaded -7 0 parts) ; updated the package information table 1, 4, 5, 9 downloaded from: http:///
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